NSE-8G™ Standard Product Data Sheet
Preliminary
Register 103H + N*20H, RXLV and DRU Control
Bit
Type
R
Function
Unused
DRU_DTMSB
Reserved
DRU_ENB
RX_ENB
Reserved
Default
Bit 31:16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
X
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A_RSTB
Reserved[4]
Reserved[3]
Reserved[2]
Reserved[1]
DRU_CTRL[3]
DRU_CTRL[2]
DRU_CTRL[1]
DRU_CTRL[0]
Reserved[0]
Unused
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These registers drives the control signals for the RXLV and DRU blocks.
After Chip reset, this Register must be set to CC34h for proper operation, See below.
DRU_CTRL[3:0]
The DRU_CTRL[3:0] bits control the DRU CTRL[3:0] inputs. The DRU_CTRL[3:0] bus is
reset to 0000, but needs to be set to 1101 following a reset for correct operation of the
NSE.
A_RSTB
The A_RSTB bit is a soft-reset for the Data Recovery Unit Analog block. Setting A_RSTB to
logic 0 will reset the block.
Reserved
The Reserved bit is set to logic 0 on reset, but needs to be set to logic one following reset
for correct operation of the NSE.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
102
PMC [ PMC-SIERRA, INC ]
