NSE-8G™ Standard Product Data Sheet
Preliminary
FIFOERRE
The FIFO underrun/overrun error interrupt enable bit (FIFOERRE) masks the contribution of
the FIFO underrun/overrun event indication bit (FIFOERRI) in the T8TE block to INTB.
When FIFOERRE is high, INTB is asserted low when FIFOERRI is high. INTB is not
affected by the value of FIFOERRI when FIFOERRE is low.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
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