PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x024 : FREEDM-84A672 Master Performance Monitor Control
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Unused
TP2EN
TABRT2EN
RP2EN
RLENE2EN
RABRT2EN
RFCSE2EN
RSPE2EN
Unused
TP1EN
TABRT1EN
RP1EN
RLENE1EN
RABRT1EN
RFCSE1EN
RSPE1EN
X
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register configures the events that are accumulated in the two configurable
performance monitor counters in the PMON block.
RSPE1EN:
The receive small packet error accumulate enable bit (RSPE1EN) enables
counting of minimum packet size violation events. When RSPE1EN is set
high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified
CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable
Accumulator #1 register to increment. Small packet errors are ignored when
RSPE1EN is set low.
RFCSE1EN:
The receive frame check sequence error accumulate enable bit (RFCSE1EN)
enables counting of receive FCS error events. When RFCSE1EN is set high,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
76
PMC [ PMC-SIERRA, INC ]
