PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x00C : FREEDM-84A672 Master Clock / Frame Pulse Activity
Monitor and Accumulation Trigger
Bit
Type
Function
Default
Bit 15
to
Unused
XH
Bit 14
Bit 13
Bit 12
R
R
TXCLKA
RXCLKA
Unused
X
X
XH
Bit 11
to
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
C1FPA
X
X
X
X
FASTCLKA
REFCLKA
SYSCLKA
This register provides activity monitoring on the FREEDM-84A672 clock and SBI
frame pulse inputs. When a monitored input makes a transition, the
corresponding register bit is set high. The bit will remain high until this register is
read, at which point, all the bits in this register are cleared. A lack of transitions is
indicated by the corresponding register bit reading low. This register should be
read periodically to detect for stuck at conditions.
Writing to this register delimits the accumulation intervals in the PMON
accumulation registers. Counts accumulated in those registers are transferred to
holding registers where they can be read. The counters themselves are then
cleared to begin accumulating events for a new accumulation interval. The bits in
this register are not affected by write accesses.
SYSCLKA:
The system clock active bit (SYSCLKA) monitors for low to high transitions on
the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is
set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
73
PMC [ PMC-SIERRA, INC ]
