PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Register 0x014 : FREEDM-84A672 Master Line Loopback
Bit
Type
Function
Default
Bit 15
to
R/W
Reserved
0000H
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
LLBEN[2]
LLBEN[1]
LLBEN[0]
0
0
0
This register controls line loopback for the three serial data links (enabled when
SPEn_EN is low).
LLBEN[2:0]:
The line loopback enable bits (LLBEN[2:0]) control line loopback for links #2
to #0. When LLBEN[n] is set high, the data on RD[n] is passed verbatim to
TD[n] which is then updated on the falling edge of RCLK[n]. TCLK[n] is
ignored. When LLBEN[n] is set low, TD[n] is processed normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
75
PMC [ PMC-SIERRA, INC ]
