PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
REFCLKA:
The SBI reference clock active bit (REFCLKA) monitors for low to high
transitions on the REFCLK input. REFCLKA is set high on a rising edge of
REFCLK, and is set low when this register is read.
FASTCLKA:
The SBI fast clock active bit (FASTCLKA) monitors for low to high transitions
on the FASTCLK input. FASTCLKA is set high on a rising edge of FASTCLK,
and is set low when this register is read.
C1FPA:
The SBI frame pulse active bit (C1FPA) monitors for low to high transitions on
the C1FP input. C1FPA is set high on a rising edge of C1FP, and is set low
when this register is read.
RXCLKA:
The Any-PHY receive clock active bit (RXCLKA) monitors for low to high
transitions on the RXCLK input. RXCLKA is set high on a rising edge of
RXCLK, and is set low when this register is read.
TXCLKA:
The Any-PHY transmit clock active bit (TXCLKA) monitors for low to high
transitions on the TXCLK input. TXCLKA is set high on a rising edge of
TXCLK, and is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
74
PMC [ PMC-SIERRA, INC ]
