PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Interrupts are masked when TFOVRE is set low. However, the TFOVRI bit
remains valid when interrupts are disabled and may be polled to detect
transmit FIFO overflow events.
TFUDRE:
The transmit FIFO underflow error interrupt enable bit (TFUDRE) enables
transmit FIFO underflow error interrupts to the microprocessor. When
TFUDRE is set high, attempts to read data from the logical FIFO when it is
already empty will cause an interrupt to be generated on the INTB output.
Interrupts are masked when TFUDRE is set low. However, the TFUDRI bit
remains valid when interrupts are disabled and may be polled to detect
transmit FIFO underflow events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
