PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Pin Name
Type
Pin
No.
Function
TERR
Input
T25
The transmit error signal (TERR) indicates that
the current packet is errored and should be
aborted. TERR is only valid when TEOP is
sampled high. When TERR is sampled high
and TEOP is sampled high, the current packet is
errored and the FREEDM-84A672 will respond
accordingly. When TERR is sampled low and
TEOP is sampled high, the current packet is not
errored. TERR must be set low when TEOP is
set low.
TERR is sampled on the rising edge of TXCLK.
RXCLK
Input
Input
AE23 The receive clock signal (RXCLK) provides
timing for the receive Any-PHY packet interface
(APPI). RXCLK is a nominally 50% duty cycle,
25 to 50 MHz clock.
RXADDR[0]
RXADDR[1]
RXADDR[2]
AF23 The receive address signals (RXADDR[2:0])
AC21 serve two functions – device polling and device
AD22 selection. When polling, the RXADDR[2:0]
signals provide an address for polling a
FREEDM-84A672 device for receive data
available in any one of its 672 channels. Polling
results are returned on the RPA tristate output.
During selection, the address on the
RXADDR[2:0] signals is qualified with the RENB
signal to select a FREEDM-84A672 device
enabling it to output data on the receive APPI.
Note that up to seven FREEDM-84A672
devices may share a single external controller
(one address is reserved as a null address).
The Rx APPI of each FREEDM-84A672 device
is identified by the base address in the RAPI672
Control register.
The RXADDR[2:0] signals are sampled on the
rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
23
PMC [ PMC-SIERRA, INC ]
