PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Pin Name
RPA
Type
Pin
No.
Function
Tristate U25
The receive packet available signal (RPA)
reflects the status of a poll on the receive APPI
of a FREEDM-84A672 device. When RPA is set
high, the polled FREEDM-84A672 device has
XFER[3:0] plus one blocks (16 bytes per block)
of data to transfer, or alternatively, a smaller
amount of data which includes an end of packet.
When RPA is set low, the polled FREEDM-
84A672 device does not have data ready to
transfer. (XFER[3:0] is a per-channel
Output
programmable value – see description of
register 0x208.)
A FREEDM-84A672 device must not be
selected for receive data transfer unless it has
been polled and responded that it has data
ready to transfer.
When the RXADDR[2:0] inputs match the base
address in the RAPI672 Control register, that
FREEDM-84A672 device drives RPA one
RXCLK cycle after sampling RXADDR[2:0].
RPA is tristate during reset and when a device
address other than the FREEDM-84A672’s base
address is provided on RXADDR[2:0].
RPA is updated on the rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
24
PMC [ PMC-SIERRA, INC ]
