PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Table 48 – Clock/Data Input (Figure 39)
Symbol
Description
Min
Max
Units
RCLK[2:0] Frequency
RCLK[2:0] Duty Cycle
RD[2:0] Set-Up Time
RD[2:0] Hold Time
51.84
60
MHz
%
ns
40
1
tS
RD
tH
2
ns
RD
Figure 39 – Receive Data Timing
RCLK[n]
tSRD
tHRD
RD[n]
Table 49 – Clock/Data Output (Figure 40)
Symbol
Description
Min
Max
Units
TCLK[2:0] Frequency
TCLK[2:0] Duty Cycle
TCLK[2:0] Low to TD[2:0] Valid
51.84
60
12
MHz
%
ns
40
3
t
P
TD
Figure 40 – Transmit Data Timing
TCLK[n]
tPTD
TD[n]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
340
PMC [ PMC-SIERRA, INC ]
