PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
17
FREEDM-84P672 TIMING CHARACTERISTICS
(T = -40°C to +85°C, V = 3.0 to 3.6 V, V = 2.3 to 2.7 V)
DD2.5
A
DD3.3
Table 45 – Clocks and SBI Frame Pulse (Figure 35)
Symbol
Description
Min
Max
Units
REFCLK Frequency
19.44
19.44
MHz
-50 ppm
+50 ppm
REFCLK Duty Cycle
40
60
%
FASTCLK Frequency (51.84 MHz)
51.84
51.84
MHz
-50 ppm
+50 ppm
FASTCLK Frequency (44.928 MHz) 44.928
44.928
MHz
MHz
-50 ppm
+50 ppm
FASTCLK Frequency (66 MHz)
66
66
-50 ppm
+50 ppm
FASTCLK Duty Cycle
SYSCLK Frequency
40
60
%
MHz
45
45
-50 ppm
+50 ppm
SYSCLK Duty Cycle
40
4
60
%
TS
TH
C1FP Set-Up Time to REFCLK
C1FP Hold Time to REFCLK
REFCLK to C1FPOUT Valid
ns
ns
ns
C1FP
1
C1FP
T
2
20
P
C1FPOUT
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
2. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
336
PMC [ PMC-SIERRA, INC ]
