PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Figure 36 – SBI DROP BUS Timing
REFCLK
tS
tH
SBIDROP
SBIDROP
DDATA[7:0]
DDP, DPL
DV5
Table 47 – SBI ADD BUS (Figure 37 to Figure 38)
Symbol
tS
Description
Min
4
Max
Units
ns
AJUST_REQ Set-Up Time to REFCLK
AJUST_REQ Hold Time to REFCLK
REFCLK to AACTIVE Valid
SBIADD
tH
1
ns
SBIADD
AACTIVE
SBIADD
t
t
2
18
20
ns
P
P
REFCLK to All SBI ADD BUS Outputs
(except AACTIVE) Valid
2
2
0
ns
ns
ns
t
t
REFCLK to All SBI ADD BUS Outputs
20
15
Z
SBIADD
(except AACTIVE) Tristate
ADETECT[1] and ADETECT[0] low to
All SBI ADD BUS Outputs (except
AACTIVE) Valid
P
OUTEN
t
ADETECT[1] or ADETECT[0] high to All
SBI ADD BUS Outputs (except
AACTIVE) Tristate
0
15
ns
Z
OUTEN
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
338
PMC [ PMC-SIERRA, INC ]
