RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Table 4 – Miscellaneous Interface Signals (9)
Pin Name Type
Pin
No.
Function
SYSCLK
RSTB
Input
Input
K23
The system clock (SYSCLK) provides timing for
the core logic. SYSCLK is nominally a 50% duty
cycle, 25 to 45 MHz clock.
C22
The active low reset signal (RSTB) signal
provides an asynchronous FREEDM-32A256
reset. RSTB is an asynchronous input. When
RSTB is set low, all FREEDM-32A256 registers
are forced to their default states. In addition,
TD[31:0] are forced high and all APPI output pins
are forced tristate and will remain high or tristated,
respectively, until RSTB is set high.
PMCTEST Input
AB3 The PMC production test enable signal
(PMCTEST) places the FREEDM-32A256 is test
mode. When PMCTEST is set high, production
test vectors can be executed to verify
manufacturing via the test mode interface signals
TA[11:0], TA[12]/TRS, TRDB, TWRB and
TDAT[15:0]. PMCTEST must be tied low for
normal operation.
TCK
TMS
TDI
Input
Input
Input
T23
T22
U21
The test clock signal (TCK) provides timing for
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS and TDI are
sampled on the rising edge of TCK. TDO is
updated on the falling edge of TCK.
The test mode select signal (TMS) controls the
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS is sampled
on the rising edge of TCK. TMS has an integral
pull up resistor.
The test data input signal (TDI) carries test data
into the FREEDM-32A256 via the IEEE P1149.1
test access port. TDI is sampled on the rising
edge of TCK.
TDI has an integral pull up resistor.
PROPRIETARY AND CONFIDENTIAL
37
PMC [ PMC-SIERRA, INC ]
