RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Table 5 – Production Test Interface Signals (0 - Multiplexed)
Pin Name Type
Pin
No.
Function
TA[0]
TA[1]
TA[2]
TA[3]
TA[4]
TA[5]
TA[6]
TA[7]
TA[8]
TA[9]
TA[10]
TA[11]
Input
G23
F23
E23
D22
E20
C23
A22
D20
B21
D19
B20
A19
The test mode address bus (TA[11:0]) selects
specific registers during production test
(PMCTEST set high) read and write accesses.
TA[11:0] replace RD[21:10] when PMCTEST is
set high.
TA[12]/
TRS
Input
Input
A16
The test register select signal (TA[12]/TRS)
selects between normal and test mode register
accesses during production test (PMCTEST set
high). TRS is set high to select test registers and
is set low to select normal registers. TA[12]/TRS
replaces RD[24] when PMCTEST is set high.
TRDB
TWRB
A18
The test mode read enable signal (TRDB) is set
low during FREEDM-32A256 register read
accesses during production test (PMCTEST set
high). The FREEDM-32A256 drives the test data
bus (TDAT[15:0]) with the contents of the
addressed register while TRDB is low. TRDB
replaces RD[22] when PMCTEST is set high.
Input
A17
The test mode write enable signal (TWRB) is set
low during FREEDM-32A256 register write
accesses during production test (PMCTEST set
high). The contents of the test data bus
(TDAT[15:0]) are clocked into the addressed
register on the rising edge of TWRB. TWRB
replaces RD[23] when PMCTEST is set high.
PROPRIETARY AND CONFIDENTIAL
39
PMC [ PMC-SIERRA, INC ]
