RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Pin
No.
Function
TD[31:0] are updated on the falling edge of
the corresponding TCLK[31:0] clock.
TMVCK[0]
TMVCK[1]
TMVCK[2]
TMVCK[3]
Input
V21
The transmit MVIP data clock signals
(TMVCK[3:0]) provide the transmit data
clocks for the 32 links when configured to
operate in 2.048 Mbps H-MVIP mode.
Y19
AA15
AB9
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share
a common clock. TMVCK[0], TMVCK[1],
TMVCK[2] and TMVCK[3] update the data
on links TD[7:0], TD[15:8], TD[23:16] and
TD[31:24] respectively. Each TMVCK[n] is
nominally a 50% duty cycle clock with a
frequency of 4.096 MHz.
TMVCK[n] is unused and should be tied low
when no physical links within the associated
group of 8 logical links is configured for
operation in 2.048 Mbps H-MVIP mode.
TFPB[0]
TFPB[1]
TFPB[2]
TFPB[3]
Input
V23
The transmit frame pulse signals
(TFPB[3:0]) reference the beginning of each
frame when configured for operation in
2.048 Mbps H-MVIP mode.
AA20
AB15
AA9
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share
a common frame pulse. TFPB[0], TFPB[1],
TFPB[2] and TFPB[3] reference the
beginning of a frame on links TD[7:0],
TD[15:8], TD[23:16] and TD[31:24]
respectively.
When configured for operation in 2.048
Mbps H-MVIP mode, TFPB[n] is sampled on
the falling edge of TMVCK[n]. Otherwise,
TFPB[n] is ignored and should be tied low.
PROPRIETARY AND CONFIDENTIAL
20
PMC [ PMC-SIERRA, INC ]
