RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Output
Pin
No.
Function
TD[0]
W23
The transmit data signals (TD[31:0]) contain
the transmit data for the 32 independently
timed links in normal mode (PMCTEST set
low). Processing of the transmit links is on
a priority basis, in descending order from
TD[0] to TD[31]. Therefore, the highest rate
link should be connected to TD[0] and the
lowest to TD[31].
TD[1]
Y22
TD[2]
W20
AA22
Y20
TD[3]
TD[4]
TD[5]
AB23
AC22
AC21
AC20
AA19
AA18
AB18
Y17
TD[6]
TD[7]
TD[8]
For H-MVIP links, TD[n] contain 32/128
time-slots, depending on the H-MVIP data
rate configured (2.048 or 8.192 Mbps).
When configured for 2.048 Mbps H-MVIP
operation, TD[31:24], TD[23:16], TD[15:8]
and TD[7:0] are updated on every 2nd falling
edge of TMVCK[3], TMVCK[2], TMVCK[1]
and TMVCK[0] respectively. When
TD[9]
TD[10]
TD[11]
TD[12]
TD[13]
TD[14]
TD[15]
TD[16]
TD[17]
TD[18]
TD[19]
TD[20]
TD[21]
TD[22]
TD[23]
TD[24]
TD[25]
TD[26]
TD[27]
TD[28]
TD[29]
TD[30]
TD[31]
AA17
AB16
AC15
AC14
AA14
AC13
AB13
AA12
AB11
Y11
configured for 8.192 Mbps H-MVIP
operation, TD[4m] (0?m?7) are updated on
every 2nd falling edge of TMV8DC.
For channelised links, TD[n] contains the 24
(T1/J1) or 31 (E1) time-slots that comprise
the channelised link. TCLK[n] must be
gapped during the T1/J1 framing bit position
or during the E1 frame alignment signal
(time-slot 0). The FREEDM-32A256 uses
the location of the gap to determine the
channel alignment on TD[n]. TD[31:0] are
updated on the falling edge of the
AB10
Y9
AA8
AC8
AB7
AC7
corresponding TCLK[31:0].
AC6
AC5
For unchannelised links, TD[n] contains the
HDLC packet data. For certain transmission
formats, TD[n] may contain place holder bits
or time-slots. TCLK[n] must be externally
gapped during the place holder positions in
the TD[n] stream. The FREEDM-32A256
supports a maximum data rate of 10 Mbit/s
on an individual TD[31:3] link and a
maximum data rate of 51.84 Mbit/s on
TD[2:0].
AB4
PROPRIETARY AND CONFIDENTIAL
19