RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x014 : FREEDM-32A256 Master Line Loopback #1
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LLBEN[15]
LLBEN[14]
LLBEN[13]
LLBEN[12]
LLBEN[11]
LLBEN[10]
LLBEN[9]
LLBEN[8]
LLBEN[7]
LLBEN[6]
LLBEN[5]
LLBEN[4]
LLBEN[3]
LLBEN[2]
LLBEN[1]
LLBEN[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register controls line loopback for links #0 to #15.
LLBEN[15:0]:
The line loopback enable bits (LLBEN[15:0]) controls line loopback for
links #15 to #0. When links #0 through #15 are configured for channelised
T1/J1/E1 or unchannelised traffic and LLBEN[n] is set high, the data on RD[n]
is passed verbatim to TD[n] which is then updated on the falling edge of
RCLK[n]. TCLK[n] is ignored. When LLBEN[n] is set low, TD[n] is processed
normally. Line loopback is not supported for H-MVIP traffic.
PROPRIETARY AND CONFIDENTIAL
85
PMC [ PMC-SIERRA, INC ]
