RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x020 : FREEDM-32A256 Master BERT Control
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
TBEN
Unused
Unused
TBSEL[4]
TBSEL[3]
TBSEL[2]
TBSEL[1]
TBSEL[0]
RBEN
0
X
X
0
0
0
0
0
0
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Unused
Unused
Bit 4
Bit 3
Bit 2
Bit 1
R/W
R/W
R/W
R/W
R/W
RBSEL[4]
RBSEL[3]
RBSEL[2]
RBSEL[1]
RBSEL[0]
Bit 0
This register controls the bit error rate testing of the receive and transmit links.
Bit error rate testing is not supported for links configured for H-MVIP traffic.
RBSEL[4:0]:
The receive bit error rates testing link select bits (RBSEL[4:0]) controls the
source of data on the RBD and RBCLK outputs when receive bit error rate
testing is enabled (RBEN set high). RBSEL[4:0] is a binary number that
selects a receive link configured for non H-MVIP traffic (RD[31:0]/RCLK[31:0])
to be the source of data for RBD and RBCLK outputs. RBSEL[4:0] is ignored
when RBEN is set low. RBSEL[4:0] cannot select a link configured for H-
MVIP traffic.
PROPRIETARY AND CONFIDENTIAL
88
PMC [ PMC-SIERRA, INC ]
