RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x50C : PMON Configurable Count #1
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
C1[15]
C1[14]
C1[13]
C1[12]
C1[11]
C1[10]
C1[9]
C1[8]
C1[7]
C1[6]
C1[5]
C1[4]
C1[3]
C1[2]
C1[1]
C1[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register reports the number events, selected by the FREEDM-32A256
Master Performance Monitor Control register, that occurred in the previous
accumulation interval.
C1[15:0]:
The C1[15:0] bits reports the number of selected events that have been
detected since the last time this register was polled. This register is polled by
writing to the FREEDM-32A256 Master Clock / BERT Activity Monitor and
Accumulation Trigger register. The write access transfers the internally
accumulated error count to the configurable count #1 register and
simultaneously resets the internal counter to begin a new cycle of event
accumulation.
PROPRIETARY AND CONFIDENTIAL
149
PMC [ PMC-SIERRA, INC ]
