RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x504 : PMON Receive FIFO Overflow Count
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
OF[15]
OF[14]
OF[13]
OF[12]
OF[11]
OF[10]
OF[9]
OF[8]
OF[7]
OF[6]
OF[5]
OF[4]
OF[3]
OF[2]
OF[1]
OF[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register reports the number of receive FIFO overflow events in the previous
accumulation interval.
OF[15:0]:
The OF[15:0] bits reports the number of receive FIFO overflow events that
have been detected since the last time this register was polled. This register
is polled by writing to the FREEDM-32A256 Master Clock / BERT Activity
Monitor and Accumulation Trigger register. The write access transfers the
internally accumulated error count to the FIFO overflow register and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
PROPRIETARY AND CONFIDENTIAL
147
PMC [ PMC-SIERRA, INC ]
