RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x510 : PMON Configurable Count #2
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
C2[15]
C2[14]
C2[13]
C2[12]
C2[11]
C2[10]
C2[9]
C2[8]
C2[7]
C2[6]
C2[5]
C2[4]
C2[3]
C2[2]
C2[1]
C2[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register reports the number events, selected by the FREEDM-32A256
Master Performance Monitor Control register, that occurred in the previous
accumulation interval.
C2[15:0]:
The C2[15:0] bits reports the number of selected events that have been
detected since the last time this register was polled. This register is polled by
writing to the FREEDM-32A256 Master Clock / BERT Activity Monitor and
Accumulation Trigger register. The write access transfers the internally
accumulated error count to the configurable count #2 register and
simultaneously resets the internal counter to begin a new cycle of event
accumulation.
PROPRIETARY AND CONFIDENTIAL
150
PMC [ PMC-SIERRA, INC ]
