RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x580 : RAPI Control
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
R/W
R/W
R/W
ENABLE
STATEN
Reserved
Unused
0
0
0
Bit 12
to
XXXH
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
ALL1ENB
BADDR[2]
BADDR[1]
BADDR[0]
1
1
1
1
This register provides the base address of the Rx APPI for purposes of
responding to polling and device selection. This register also enables the
RAPI256.
BADDR[2:0]:
The base address bits (BADDR[2:0]) configure the address space occupied
by the FREEDM-32A256 device for purposes of responding to receive polling
and receive device selection. During polling, the BADDR[2:0] bits are used to
respond to polling via the RXADDR[2:0] pins. During device selection, the
BADDR[2:0] are used to select a FREEDM-32A256 device, enabling it to
accept data on the receive APPI. During data transfer, the RXDATA[15:13]
pins of the prepended channel address reflect the BADDR[2:0] bits.
ALL1ENB:
The All Ones Enable bit (ALL1ENB) permits the FREEDM-32A256 to respond
to receive polling and device selection when BADDR[2:0] = ‘111’. When
ALL1ENB is zero, the FREEDM-32A256 responds to receive polling and
device selection when BADDR[2:0] = RXADDR[2:0] = ‘111’. When ALL1ENB
is one, the FREEDM-32A256 regards the all-ones address as a null address
and does not respond to receive polling and device selection when
BADDR[2:0] = ‘111’, regardless of the value of RXADDR[2:0].
PROPRIETARY AND CONFIDENTIAL
151
PMC [ PMC-SIERRA, INC ]
