RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x600 : TAPI Control
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
R/W
R/W
R/W
ENABLE
Reserved
Reserved
Unused
0
0
0
Bit 12
to
XXXH
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
ALL1ENB
BADDR[2]
BADDR[1]
BADDR[0]
1
1
1
1
This register provides the base address of the Tx APPI for purposes of
responding to polling and Tx APPI data transfers. This register also enables the
TAPI256.
BADDR[2:0]:
The base address bits (BADDR[2:0]) configure the address space occupied
by the FREEDM-32A256 device for purposes of responding to transmit polling
and transmit data transfers. During polling, the TXADDR[12:10] pins are
compared with the BADDR[2:0] bits to determine if the poll address identified
by TXADDR[9:0] is intended for a channel in this FREEDM-32A256 device.
During data transmission, the TXDATA[15:13] pins of the prepended channel
address are compared with the BADDR[2:0] bits to determine if the data to
follow is intended for this FREEDM-32A256 device.
ALL1ENB:
The All Ones Enable bit (ALL1ENB) permits the FREEDM-32A256 to respond
to transmit polling and device selection when BADDR[2:0] = ‘111’. When
ALL1ENB is zero, the FREEDM-32A256 responds to transmit polling when
BADDR[2:0] = TXADDR[12:10] = ‘111’ and device selection when
BADDR[2:0] = TXDATA[15:13] = ‘111’. When ALL1ENB is one, the FREEDM-
32A256 regards the all-ones address as a null address and does not respond
to transmit polling and device selection when BADDR[2:0] = ‘111’, regardless
of the values of TXADDR[12:10] and TXDATA[15:13].
PROPRIETARY AND CONFIDENTIAL
153
PMC [ PMC-SIERRA, INC ]
