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PM7383 参数 Datasheet PDF下载

PM7383图片预览
型号: PM7383
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
Table 15 – Transmit Links #0 to #2 Configuration  
MODE[2:0]  
Link Configuration  
000  
001  
010  
011  
100  
101  
110  
111  
Unchannelised  
Channelised T1/J1 (24 time slots labeled 1-24)  
Channelised E1 (31 time slots labeled 1-31)  
2 Mbps H-MVIP (32 time slots labeled 0-31)  
Reserved  
Reserved  
Reserved  
8 Mbps H-MVIP (128 time slots mapped to time-  
slots 0 through 31 of links 4m, 4m+1, 4m+2 and  
4m+3)  
BSYNC:  
The byte synchronization enable bit (BSYNC) controls the interpretation of  
gaps in TCLK[n] when link #n is in unchannelised mode (MODE[2:0]=”000”).  
When BSYNC is set high, the data bit on TD[n] clocked in by a downstream  
device on the first rising edge of TCLK[n] after an extended quiescent period  
is considered to be the most significant bit of a data byte. When BSYNC is  
set quiescent, gaps in TCLK[n] carry no special significance. BSYNC is  
ignored when MODE[2:0]U”000”.  
PROPRIETARY AND CONFIDENTIAL  
143