RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
target and master blocks operate independent of each other. The error/bus
control block monitors the control signals from the target and master blocks to
determine the state of the PCI I/O pads. This block also generates and/or
checks parity for all data going to or coming from the PCI bus. The internal
microprocessor bus interface block contains configuration and status registers
together with the production test logic for the GPIC block.
9.6.1 Master Machine
The GPIC master machine translates requests from the RMAC672 and
TMAC672 block interfaces into PCI bus transactions. The GPIC initiates four
types of PCI cycles: memory read (burst or single), memory read multiple,
memory read line and memory write (burst or single). The number of data
transfers in any cycle is controlled by the DMA controllers. The maximum burst
size is determined by the particular data path. A read cycle to the RMAC672 is
restricted to a maximum burst size of 8 dwords and a write cycle is limited to a
maximum of 64. The TMAC672 interface has a limit of 64 dwords on a read
cycle and 8 on a write cycle.
In response to a DMA controller requesting a cycle, the GPIC must arbitrate for
control of the PCI bus. In the event that the RMAC672 and TMAC672 request
service simultaneously, the GPIC66 processes the RMAC672 DMA operation
first.
When an external PCI bus arbitrator issues a Grant in response to the Request
from the GPIC, the master state machine monitors the PCI bus to insure that the
previous master has completed its transaction and has released the bus before
beginning the cycle. Once the GPIC has control of the bus, it will assert the
FRAME signal and drive the bus with the address and command. The value for
the address is provided by the selected DMA controller. After the initial data
transfer, the GPIC tracks the address for all remaining transfers in the burst
internally in case the GPIC is disconnected by the target and must retry the
transaction.
The target of the GPIC master burst cycle has the option of stopping or
disconnecting the burst at any point. In the event of a target disconnect the
GPIC will terminate the present cycle and release the PCI bus. If the GPIC is
asserting the REQUEST line at the time of the disconnect, it will remove the
REQUEST for two PCI clock cycles then reassert it. When the PCI bus arbitrator
returns the GRANT, the GPIC will restart the burst access at the next address
and continue until the burst is completed or repeat the sequence if the target
disconnects again.
During burst reads, the GPIC accepts the data without inserting any wait states.
Data is written directly into the read FIFO where the RMAC672 or TMAC672 can
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
58
PMC [ PMC-SIERRA, INC ]
