RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
remove it at its own rate. During burst writes, the GPIC will output the data
without inserting any wait states, but may terminate the transaction early if the
local master fails to fill the write FIFO with data before the GPIC requires it. (If a
write transaction is terminated early due to data starvation, the GPIC will
automatically initiate a further transaction to write the remaining data when it
becomes available.)
Normally, the GPIC will begin requesting the PCI bus for a write transaction
shortly after data starts to be loaded into the write FIFO by the RMAC672 or
TMAC672. The RMAC672, however, is not required to supply a transaction
length when writing packet data and in addition, may insert pauses during the
transfer. In the case of packet data writes by the RMAC672, the GPIC will hold
off requesting the PCI bus until the write FIFO has filled up with a number of
dwords equal to a programmable threshold. If the FIFO empties without
reaching the end of the transition, the GPIC will terminate the current transaction
and restart a new transaction to transfer any remaining data when the RMAC672
signals an end of transaction. Beginning the PCI transaction before all the data
is in the write FIFO allows the GPIC to reduce the impact of the bus latency on
the core device.
Each master PCI cycle generated by the GPIC can be terminated in three ways:
Completion, Timeout or Master Abort. The normal mode of operation of the GPIC
is to terminate after transferring all the data from the master FIFO selected. As
noted above this may involve multiple PCI accesses because of the inability of
the target to accept the full burst or data starvation during writes. After the
completion of the burst transfer the GPIC will release the bus unless another
FIFO is requesting service, in which case if the GRANT is asserted the GPIC will
insert one idle cycle on the bus and then start a new transfer.
The maximum duration of the a master burst cycle is controlled by the value set
in the LATENCY TIMER register in the GPIC Configuration Register block. This
value is set by the host on boot and is loaded into a counter in the GPIC master
state at the start of each access. If the counter reaches zero and the GRANT
signal has been removed the GPIC will release the bus regardless of whether it
has completed the present burst cycle. This type of termination is referred to as
a Master Time-out. In the case of a Master Time-out the GPIC will remove the
REQUEST signal for two PCI clocks and then reassert it to complete the burst
cycle.
If no target responds to the address placed on the bus by the GPIC after 4 PCI
clocks the GPIC will terminate the cycle and flag the cycle in the PCI Command/
Status Configuration Register as a Master Abort. If the Stop on Error enable
(SOE_E) bit is set in the GPIC Command Register, the GPIC will not process any
more requests until the error condition is cleared. If the SOE_E is not set, the
GPIC will discard the REQUEST and indicate to the local master that the cycle is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
59
PMC [ PMC-SIERRA, INC ]
