RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
9.5.5 Free Queue Cache
The Free Queue Cache block implements the 6 element RPDR Small Buffer
Free Queue cache and the 6 element RPDR Large Buffer Free Queue cache.
These caches are used to store free small buffer and large buffer RPDRs.
Caching RPDRs reduces the number of host bus accesses that the RMAC672
makes.
Each cache is managed independently. The elements of the cache are
consumed one at a time as they are needed by the RMAC672. The RPDR small
buffer cache is reloaded when it is empty and the RMAC672 requires a new
small buffer RPDR. The large buffer RPDR cache is reloaded when it is empty
and the RMAC672 requires a new large buffer RPDR. When reloading either of
the caches, the appropriate cache controller will read up to six new elements.
The cache controller may read fewer than six elements if there are fewer than six
new elements available, or the read pointer index is within six elements of the
end of the free queue. If the read pointer is near the end of the free queue, the
cache controller reads only to the end of the queue and does not start reading
from the top of the queue until the next time a reload is required. To do so would
require two host memory transactions and would be of no benefit.
9.6 PCI Controller
The General-Purpose Peripheral Component Interconnect Controller block
(GPIC) provides a 32-bit Master and Target interface core which contains all the
required control functions for full Peripheral Component Interconnect (PCI) Bus
Revision 2.1 compliance. Communications between the PCI bus and other
FREEDM-32P672 blocks can be made through either an internal
asynchronous16-bit bus or through one of two synchronous FIFO interfaces.
One of the FIFO interfaces is dedicated to servicing the Receive DMA Controller
block (RMAC672) and the other to the Transmit DMA Controller block
(TMAC672).
The GPIC supports a 32-bit PCI bus operating at up to 66 MHz and bridges
between the timing domain of the DMA controllers (SYSCLK) and the timing
domain of the PCI bus (PCICLK). The GPIC is backwards compatible and will
operate at 33 MHz when connected to a 33 MHz PCI bus. By itself, the GPIC
does not generate any PCI bus accesses. All transactions on the bus are
initiated by another PCI bus master or by the core device. The GPIC transforms
each access to and from the PCI bus to the intended target or initiator in the core
device. Except for the configuration space registers and parity
generating/checking, the GPIC performs no operations on the data.
The GPIC is made up of four sections: master state machine, a target state
machine, internal microprocessor bus interface and error/bus controller. The
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
