RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Field
Description
Buffer Size[14:0]
This field contains the size in bytes of the buffer
currently being written to.
V
This bit (Valid) indicates whether a packet is currently
being received on the DMA channel. When the V bit is
set to 1, the other fields in the RCDR table entry for the
DMA channel contain valid information.
Start RPD
This field contains the pointer to the first RPD for the
Pointer[14:0]
packet being received.
DMA Current
The DMA Current Address [31:0] bits holds the host
address of the next dword in the current buffer. The
RMAC672 increments this field on each access to the
buffer.
Address[31:0]
9.5.2 DMA Transaction Controller
The DMA Transaction Controller coordinates the reception of data packets from
the Receive Packet Interface and their subsequent storage in host memory. A
packet may be received over a number of separate transactions, interleaved with
transactions belonging to other DMA channels. As well as sending the received
data to host memory, the DMA Transaction Controller initiates data transactions
of its own for the purposes of maintaining the data structures (queues,
descriptors, etc.) in host memory.
9.5.3 Write Data Pipeline/Mux
The Write Data Pipeline/Mux performs two functions. First, it pipelines receive
data between the RHDL672 block and the GPIC block, inserting enough delay to
enable the DMA Transaction Controller to generate appropriate control signals at
the GPIC interface. Second, it provides a multiplexor to the data out lines on the
GPIC interface, allowing the DMA Transaction Controller to output data relating
to the transactions the controller itself initiates.
9.5.4 Descriptor Information Cache
The Descriptor Information Cache provides the storage for the Receive Channel
Descriptor Reference (RCDR) Table described above (Figure 9).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
56
PMC [ PMC-SIERRA, INC ]
