RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Although a STATUS+RPDR only totals to 17 bits, each queue entry is a dword,
i.e. 32 bits. When the RMAC672 block writes a STATUS+RPDR to the ready
queue, it sets the remaining 7 bits in the third byte to zero and the fourth byte is
unmodified.
Figure 8 – RPDRR Queue Operation
Rx Packet Descriptor Reference Ready Queue
Bit 31
Bit 0
RPDRRQ_START_ADDR
RPDRRQ_READ_ADDR
buffer
-packet M
RPD - 16 bytes
RPD - 16 bytes
STATUS+RPDR
STATUS+RPDR
STATUS+RPDR
buffer
-packet N
RPDRRQ_W RITE_ADDR
RPD - 16 bytes
RPD - 16 bytes
RPD - 16 bytes
buffer
-start of
packet O
buffer
-middle of
packet O
buffer
-end of
packet O
RPDRRQ_END_ADDR
Receive Channel Descriptor Reference Table
On a per-channel basis, the RMAC672 caches information such as the current
DMA information in a Receive Channel Descriptor Reference (RCDR) Table.
The RMAC672 can process 672 channels and stores three dwords of
information per channel. This information is cached internally in order to
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
54
PMC [ PMC-SIERRA, INC ]
