RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Figure 7 – RPDRF and RPDRR Queues
Receive Packet Descriptor (RPD) Reference Queues
Base Address:
RQB[31:2] = Rx Queue Base register
Index Registers:
Small Buffer Free Queue:
Large Buffer Free Queue:
RPDRLFQS[15:0] RPDR Large Free Queue Start register
RPDRLFQW [15:0] = RPDR Large Free Queue W rite register
=
RPDRSFQS[15:0]
=
RPDR Small Free Queue Start register
RPDRSFQW [15:0] = RPDR Small Free Queue W rite register
RPDRLFQR[15:0]
RPDRLFQE[15:0]
=
=
RPDR Large Free Queue Read register
RPDR Large Free Queue End register
RPDRSFQR[15:0]
RPDRSFQE[15:0]
=
=
RPDR Small Free Queue Read register
RPDR Small Free Queue End register
Ready Queue:
RPDRRQS[15:0]
RPDRRQW [15:0]
RPDRRQR[15:0]
RPDRRQE[15:0]
=
RPDR Ready Queue Start register
RPDR Ready Queue W rite register
RPDR Ready Queue Read register
RPDR Ready Queue End register
=
Base Address
Index Register
RQB[31:2]
Index[15:0]
00
00
=
=
+
+
-------------------------
Host Address
AD[31:0]
Rx Packet Descriptor Reference Queue Memory Map
Bit 31
Bit 0
RPDRRQS
RPDRRQR
Status + RPDR
Status + RPDR
Status + RPDR
Host Memory
Status + RPDR
Status + RPDR
Status + RPDR
RPDRRQW
RPDRRQE
RQB
RPDRLFQS
RPDRLFQR
RPDR
RPDR
RPDR
256KB
RPD Reference Queues
RPDR
RPDR
RPDR
RPDRLFQW
RPDRLFQE
RPDRSFQS
RPDRSFQR
RPDR
RPDR
RPDR
Valid RPDR
RPDR
RPDR
RPDR
RPDRSFQW
RPDRSFQE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
52
PMC [ PMC-SIERRA, INC ]
