RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
9.3.2 Line Interface
There are 32 identical line interface blocks in the RCAS672. Each line interface
block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and
the other H-MVIP streams. Based on configuration, only one of the sub-blocks
are active at one time; the other is held reset. Each sub-block contains a bit
counter, an 8-bit shift register and a holding register. Each sub-block performs
serial to parallel conversion. Whenever the holding register is updated, a
request for service is sent to the priority encoder block. When acknowledged by
the priority encoder, the line interface would respond with the data residing in the
holding register in the active sub-block.
To support H-MVIP links, each line interface block contains a time-slot counter.
The time-slot counter is incremented each time the holding register is updated.
When a frame pulse occurs, the time-slot counter is initialised to indicate that the
next bit is the most significant bit of the first time-slot.
To support non H-MVIP channelised links, each line interface block contains a
time-slot counter and a clock activity monitor. The time-slot counter is
incremented each time the holding register is updated. The clock activity monitor
is a counter that increments at the system clock (SYSCLK) rate and is cleared by
a rising edge of the receive clock (RCLK[n]). A framing bit (T1/J1) or a framing
byte (E1) is detected when the counter reaches a programmable threshold, in
which case, the bit and time-slot counters are initialised to indicate that the next
bit is the most significant bit of the first time-slot. For unchannelised links, the
time-slot counter and the clock activity monitor are held reset.
9.3.3 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises
them to the SYSCLK timing domain. Requests are serviced on a fixed priority
scheme where highest to lowest priority is assigned from the line interface
attached to RD[0] to that attached to RD[31]. Thus, simultaneous requests from
RD[m] will be serviced ahead of RD[n], if m < n. When there are no pending
requests, the priority encoder generates an idle cycle. In addition, once every
fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests
are serviced. This cycle is used by the channel assigner downstream for host
microprocessor accesses to the provisioning RAMs.
9.3.4 Channel Assigner
The channel assigner block determines the channel number of the data byte
currently being processed. The block contains a 1024 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
42
PMC [ PMC-SIERRA, INC ]
