RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
one flag byte must exist between HDLC packets for delineation. Contiguous flag
bytes, or all ones bytes between packets are used as an "inter-frame time fill".
Adjacent flag bytes may share zeros.
Figure 2 – HDLC Frame
Flag
Information
HDLC Packet
FCS
Flag
Flag
The CRC algorithm for the frame checking sequence (FCS) field is either a
CRC-CCITT or CRC-32 function. Figure 3 shows a CRC encoder block diagram
2
n-1
n
using the generating polynomial g(X) = 1 + g X + g X +…+ g X
n-1
+ X . The
1
2
CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 +
5
12
16
X + X + X . The CRC-32 FCS is four bytes in size and has a generating
2
4
5
7
8
10
11
12
16
22
polynomial g(X) = 1 + X + X + X + X + X + X + X + X + X + X + X
23
26
32
+ X + X + X . The first FCS bit received is the residue of the highest term.
Figure 3 – CRC Generator
g
g
g
n-1
1
2
Message
D
D
D
D
n-1
0
1
2
LSB
Parity Check Digits
MSB
9.3 Receive Channel Assigner
The Receive Channel Assigner block (RCAS672) processes up to 32 serial links.
Links may be configured to support 2.048 or 8.192 Mbps H-MVIP traffic, to
support T1/J1/E1 channelised traffic or to support unchannelised traffic. When
configured to support 2.048 Mbps H-MVIP traffic, each group of 8 links share a
clock and frame pulse. All links configured for 8.192 Mbps H-MVIP traffic share
a common clock and frame pulse. For T1/J1/E1 channelised traffic or for
unchannelised traffic, each link is independent and has its own associated clock.
For each link, the RCAS672 performs a serial to parallel conversion to form data
bytes. The data bytes are multiplexed, in byte serial format, for delivery to the
Receive HDLC Processor / Partial Packet Buffer block (RHDL672) at SYSCLK
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
39
PMC [ PMC-SIERRA, INC ]
