RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
number and the time-slot number of the current data byte. The fields of each
RAM word include the channel number and a time-slot enable flag. The time-slot
enable flag labels the current time-slot as belonging to the channel indicted by
the channel number field.
9.3.5 Loopback Controller
The loopback controller block implements the channel based diagnostic
loopback function. Every valid data byte belonging to a channel with diagnostic
loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer
block (THDL672) is written into a 64 word FIFO. The loopback controller
monitors for an idle time-slot or a time-slot carrying a channel with diagnostic
loopback enabled. If either conditions hold, the current data byte is replaced by
data retrieved from the loopback data FIFO.
9.4 Receive HDLC Processor / Partial Packet Buffer
The Receive HDLC Processor / Partial Packet Buffer block (RHDL672)
processes up to 672 synchronous transmission HDLC data streams. Each
channel can be individually configured to perform flag sequence detection, bit
de-stuffing and CRC-CCITT or CRC-32 verification. The packet data is written
into the partial packet buffer. At the end of a frame, packet status including CRC
error, octet alignment error and maximum length violation are also loaded into
the partial packet buffer. Alternatively, a channel can be provisioned as
transparent, in which case, the HDLC data stream is passed to the partial packet
buffer processor verbatim.
There is a natural precedence in the alarms detectable on a receive packet.
Once a packet exceeds the programmable maximum packet length, no further
processing is performed on it. Thus, octet alignment detection, FCS verification
and abort recognition are squelched on packets with a maximum length violation.
An abort indication squelches octet alignment detection, minimum packet length
violations, and FCS verification. In addition, FCS verification is only performed
on packets that do not have octet alignment errors, in order to allow the
RHDL672 to perform CRC calculations on a byte-basis.
The partial packet buffer is an 32 Kbyte RAM that is divided into 16-byte blocks.
Each block has an associated pointer which points to another block. A logical
FIFO is created for each provisioned channel by programming the block pointers
to form a circular linked list. A channel FIFO can be assigned a minimum of 3
blocks (48 bytes) and a maximum of 2048 blocks (32 Kbytes). The depth of the
channel FIFOs are monitored in a round-robin fashion. Requests are made to
the Receive DMA Controller block (RMAC672) to transfer, to the PCI host
memory, data in channel FIFOs with depths exceeding their associated
threshold.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
43
PMC [ PMC-SIERRA, INC ]
