RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
channel. For the case of a mixture of channelised, unchannelised and H-MVIP
links, the total instantaneous link rate over all the links is limited to 64 MHz. The
RCAS672 performs a table lookup using only the link number to determine the
associated channel, as time-slots are non-existent in unchannelised links.
The RCAS672 provides diagnostic loopback that is selectable on a per channel
basis. The RCAS672 does not support diagnostic loopback for links configured
as H-MVIP. When a channel is in diagnostic loopback, stream data on the
received links originally destined for that channel is ignored. Transmit data of
that channel is substituted in its place.
9.3.1 Line Interface Translator (LIT)
The LIT block translates the information on the 32 physical links into a suitable
format for interpretation by the Line Interface block. The LIT block performs
three functions: data translation, clock translation and frame pulse generation.
When link 4m (0?m?7) is configured for operation in 8.192 Mbps H-MVIP mode,
the LIT block translates the 128 time-slots on link 4m to the Line Interface block
across links 4m, 4m+1, 4m+2 and 4m+3. The LIT block provides time-slots 0
through 31, 32 through 63, 64 through 95 and 96 through 127 to the Line
Interface block on links 4m, 4m+1, 4m+2 and 4m+3 respectively. When link 4m
is configured for operation in 8.192 Mbps H-MVIP mode, data cannot be
received on inputs RD[4m+3:4m+1]. However, links 4m+1, 4m+2 and 4m+3
must be programmed in the RCAS672 Link Configuration register for 8.192 Mbps
H-MVIP operation. When links are configured for operation in 2.048 Mbps H-
MVIP mode, channelised T1/J1/E1 mode or unchannelised mode, the LIT block
does not perform any translation on the link data.
When a link is configured for operation in H-MVIP mode, the LIT block divides
the appropriate clock (RMVCK[n] for 2.048 Mbps H-MVIP and RMV8DC for
8.192 Mbps H-MVIP) by two and provides this divided down clock to the Line
Interface block. When a link is configured for operation in channelised T1/J1/E1
or unchannelised mode, the LIT block does not perform any translation on the
link clock.
When a link is configured for operation in H-MVIP mode, the LIT block samples
the appropriate frame pulse (RFPB[n] for 2.048 Mbps H-MVIP and RFP8B for
8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface
block. When a link is configured for operation in channelised T1/J1/E1 or
unchannelised mode, the gapped clock is passed to the LIT block unmodified.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
41
PMC [ PMC-SIERRA, INC ]
