RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Figure 4 – Partial Packet Buffer Structure
Partial Packet
Buffer RAM
Block
Pointer RAM
16 bytes
16 bytes
16 bytes
16 bytes
XX
0x03
XX
Block 0
Block 1
Block 2
Block 3
Block 0
Block 1
Block 2
Block 3
0xC8
16 bytes
16 bytes
0x01
XX
Block 200
Block 200
Block 2047
Block 2047
The FIFO algorithm of the partial packet buffer processor is based on a
programmable per-channel transfer size. Instead of tracking the number of full
blocks in a channel FIFO, the processor tracks the number of transactions.
Whenever the partial packet writer fills a transfer-sized number of blocks or
writes an end-of-packet flag to the channel FIFO, a transaction is created.
Whenever the partial packet reader transmits a transfer-size number of blocks or
an end-of-packet flag to the RMAC672 block, a transaction is deleted. Thus,
small packets less than the transfer size will be naturally transferred to the
RMAC672 block without having to precisely track the number of full blocks in the
channel FIFO.
The partial packet roamer performs the transaction accounting for all channel
FIFOs. The roamer increments the transaction count when the writer signals a
new transaction and sets a per-channel flag to indicate a non-zero transaction
count. The roamer searches the flags in a round-robin fashion to decide for
which channel FIFO to request transfer by the RMAC672 block. The roamer
informs the partial packet reader of the channel to process. The reader transfers
the data to the RMAC672 until the channel transfer size is reached or an end of
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
45
PMC [ PMC-SIERRA, INC ]
