RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
PROV bit in the corresponding word of the receive channel provision RAM in the
RCAS672 block to low.
Figure 29 – Channelised E1 Receive Link Timing
RCLK[n]
B8
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
RD[n]
B6 B7
TS 31
F1 F2 F3 F4 F5 F6 F7 F8
FAS / NFAS
TS 1
TS 2
14.4 Transmit non H-MVIP Link Timing
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals
of a unchannelised link is shown in Figure 30. The transmit data is viewed as a
contiguous serial stream. There is no concept of time-slots in an unchannelised
link. Every eight bits are grouped together into a byte with arbitrary byte
alignment. Octet data is transmitted from most significant bit (B1 in Figure 30)
and ending with the least significant bit (B8 in Figure 30). Bits are updated on
the falling edge of TCLK[n]. A transmit link may be stalled by holding the
corresponding TCLK[n] quiescent. In Figure 30, bits B5 and B2 are shown to be
stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure
30, the quiescent period is shown to be a low level on TCLK[n]. A high level,
effected by extending the high phase of the previous valid bit, is also acceptable.
Gapping of TCLK[n] can occur arbitrarily without regard to byte nor frame
boundaries.
Figure 30 – Unchannelised Transmit Link Timing
TCLK[n]
B1 B2 B3 B4 B5
B6
B7 B8 B1 B2
TD[n]
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals
of a channelised T1/J1 link is shown in Figure 31. The transmit data stream is a
T1/J1 frame with a single framing bit (F in Figure 31) followed by octet bound
time-slots 1 to 24. TCLK[n] is held quiescent during the framing bit. The most
significant bit of each time-slot is transmitted first (B1 in Figure 31). The least
significant bit of each time-slot is transmitted last (B8 in Figure 31). The TD[n] bit
(B8 of TS24) before the framing bit is the least significant bit of time-slot 24. In
Figure 31, the quiescent period is shown to be a low level on TCLK[n]. A high
level, effected by extending the high phase of bit B8 of time-slot TS24, is equally
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
293
PMC [ PMC-SIERRA, INC ]
