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PM7380-PI 参数 Datasheet PDF下载

PM7380-PI图片预览
型号: PM7380-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
acceptable. In channelised T1/J1 mode, TCLK[n] can only be gapped during the  
framing bit. It must be active continuously at 1.544 MHz during all time-slot bits.  
Time-slots that are not provisioned to belong to any channel (PROV bit in the  
corresponding word of the transmit channel provision RAM in the TCAS672  
block set low) transmit the contents of the Idle Fill Time-slot Data register.  
Figure 31 – Channelised T1/J1 Transmit Link Timing  
TCLK[n]  
B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3  
TD[n]  
TS 24  
F
TS 1  
TS 2  
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals  
of a channelised E1 link is shown in Figure 32. The transmit data stream is an  
E1 frame with a singe framing byte (FAS/NFAS in Figure 32) followed by octet  
bound time-slots 1 to 31. TCLK[n] is held quiescent during the framing byte.  
The most significant bit of each time-slot is transmitted first (B1 in Figure 32).  
The least significant bit of each time-slot is transmitted last (B8 in Figure 32).  
The TD[n] bit (B8 of TS31) before the framing byte is the least significant bit of  
time-slot 31. In Figure 32, the quiescent period is shown to be a low level on  
TCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot  
31, is equally acceptable. In channelised E1 mode, TCLK[n] can only be gapped  
during the framing byte. It must be active continuously at 2.048 MHz during all  
time-slot bits. Time-slots that are not provisioned to belong to any channel  
(PROV bit in the corresponding word of the transmit channel provision RAM in  
the TCAS672 block set low) transmit the contents of the Idle Time-slot Fill Data  
register.  
Figure 32 – Channelised E1 Transmit Link Timing  
TCLK[n]  
B8  
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4  
TS 1 TS 2  
TD[n]  
B6 B7  
TS 31  
B1  
FAS / NFAS  
14.5 PCI Interface  
A PCI burst read cycle is shown In Figure 33. The cycle is valid for target and  
initiator accesses. The target is responsible for incrementing the address during  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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