RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
During clock 5, the initiator is ready to transfer the next data word so it drives the
AD[31:0] lines with the third data word and asserts IRDYB. The initiator negates
FRAMEB since this is the last data phase of this cycle. The target is still not
ready so a wait state shall be added.
During clock 6, the target is still not ready so another wait state is added.
During clock 7, the target asserts TRDYB to indicate that it is ready to complete
the transfer.
During clock 8, the target latches in the last word and negates TRDYB and
DEVSELB, having seen FRAMEB negated previously. The initiator negates
IRDYB. All of the above signals shall be driven to their inactive state in this clock
cycle except for FRAMEB which shall be tristated.
Figure 34 – PCI Write Cycle
1
2
3
4
5
6
7
8
9
PCICLK
T
FRAMEB
T
T
Address Data 1
Bus Cmd
Data 2
Data 3
AD[31:0]
C/BEB[3:0]
Byte En Byte En
Byte Enable
T
T
T
IRDYB
TRDYB
DEVSELB
The PCI Target Disconnect (Figure 35) illustrates the case when the target wants
to prematurely terminate the current cycle. Note, when the FREEDM-32P672 is
the target, it never prematurely terminates the current cycle.
A target can terminate the current cycle by asserting the STOPB signal to the
initiator. Whether data is transferred or not depends on the state of the ready
signals at the time that the target disconnects. If the FREEDM-32P672 is the
initiator and the target terminates the current access, the FREEDM-32P672 will
retry the access after two PCI bus cycles.
During clock 1, an access is in progress.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
297
PMC [ PMC-SIERRA, INC ]
