RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Figure 24 – Receive 2.048 Mbps H-MVIP Link Timing
RMVCK[n]
(4 MHz)
RFPB[n]
RD[m]
B8
TS 31
B1
B2
B3
B4
B5
B6
B7
B8
B1
TS 1
TS 0
14.2 Transmit H-MVIP Link Timing
The timing relationship of the transmit data clock (TMV8DC), frame pulse clock
(TMV8FPC), data (TD[n]) and frame pulse (TFP8B) signals of a link configured
for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure
25. The falling edges of each TMV8FPC are aligned to a falling edge of the
corresponding TMV8DC for 8.192 Mbps H-MVIP operation. The FREEDM-
32P672 samples TFP8B low on the falling edge of TMV8FPC and references
this point as the start of the next frame. The FREEDM-32P672 updates the data
provided on TD[n] on every second falling edge of TMV8DC as indicated for bit 2
(B2) of time-slot 0 (TS 0) in Figure 25. The first bit of the next frame is updated
on TD[n] on the falling TMV8DC clock edge for which TFP8B is also sampled
low. B1 is the most significant bit and B8 is the least significant bit of each octet.
Time-slots that are not provisioned to belong to any channel (PROV bit in the
corresponding word of the transmit channel provision RAM in the TCAS672
block set low) transmits the contents of the Idle Fill Time-slot Data register.
Figure 25 – Transmit 8.192 Mbps H-MVIP Link Timing
TMV8DC
(16 MHz)
TMV8FPC
(4 MHz)
TFP8B
TD[n]
B8
B1
B2
B3
B4
B5
B6
B7
B8
B1
TS 1
TS 127
TS 0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
290
PMC [ PMC-SIERRA, INC ]
