RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Figure 27 – Unchannelised Receive Link Timing
RCLK[n]
B1 B2 B3 B4 X B5 X
X X B6 B7 B8 B1 X
RD[n]
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of
a channelised T1/J1 link is shown in Figure 28. The receive data stream is a
T1/J1 frame with a single framing bit (F in Figure 28) followed by octet bound
time-slots 1 to 24. RCLK[n] is held quiescent during the framing bit. The RD[n]
data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the
framing bit is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS24)
clocked in by the last rising edge of RCLK[n] before the framing bit is the least
significant bit of time-slot 24. In Figure 28, the quiescent period is shown to be a
low level on RCLK[n]. A high level, effected by extending the high phase of bit
B8 of time-slot TS24, is equally acceptable. In channelised T1/J1 mode,
RCLK[n] can only be gapped during the framing bit. It must be active
continuously at 1.544 MHz during all time-slot bits. Time-slots can be ignored by
setting the PROV bit in the corresponding word of the receive channel provision
RAM in the RCAS672 block to low.
Figure 28 – Channelised T1/J1 Receive Link Timing
RCLK[n]
B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
RD[n]
TS 24
TS 1
TS 2
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of
a channelised E1 link is shown in Figure 29. The receive data stream is an E1
frame with a singe framing byte (F1 to F8 in Figure 29) followed by octet bound
time-slots 1 to 31. RCLK[n] is held quiescent during the framing byte. The RD[n]
data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the
framing byte is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS31)
clocked in by the last rising edge of RLCLK[n] before the framing byte is the least
significant bit of time-slot 31. In Figure 29, the quiescent period is shown to be a
low level on RCLK[n]. A high level, effected by extending the high phase of bit
B8 of time-slot TS31, is equally acceptable. In channelised E1 mode, RCLK[n]
can only be gapped during the framing byte. It must be active continuously at
2.048 MHz during all time-slot bits. Time-slots can be ignored by setting the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
292
PMC [ PMC-SIERRA, INC ]
