RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x008 : FREEDM-32P672 Master Interrupt Status
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TFUDRI
IOCI
TDFQEI
TDQRDYI
TDQFI
RPDRQEI
RPDFQEI
RPQRDYI
RPQLFI
RPQSFI
RFOVRI
RPFEI
RABRTI
RFCSEI
PERRI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SERRI
This register reports the interrupt status for various events detected or initiated
by the FREEDM-32P672. Reading this registers acknowledges and clears the
interrupts.
Note
This register is not byte addressable. Reading this register clears all the interrupt
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
96
PMC [ PMC-SIERRA, INC ]
