RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
end’s corresponding Receive High-Speed Serial Configuration register have
been programmed to include them1.
Other than what has already been mentioned, there are no constraints on the
contents of cells written by the microprocessor. They are transported across the
LVDS link transparently. Specifically, although the standard ATM header bytes
H1-H5 are shown in Fig. 7 there is no restriction on the values they can contain.
See the Operation section for details on the cell write protocol.
1
Obviously the near and far end must configure their corresponding High-Speed Serial Configuration
registers such that the high speed link format is the same at both transmitter and receiver or the receiver
will always be out of frame.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
49
PMC [ PMC-SIERRA, INC ]
