RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
0x180 –
Reserved
Reserved for test registers.
0x1FF
0x200 –
0x3FF
9.8.1 Per-Link Registers
Each pair of serial links (RXDn+/- and TXDn+/-) has a identical bank of registers.
These registers are located within the address space by a base address and
offset according to the following formula:
register address = 0x080 + 0x20*(link index) + offset
where the link index = 0..7
Address
Offset
0x000
0x001
0x002
0x003
0x004
0x005
0x006
0x007
0x008
0x009
0x00A
0x00B
Register
Receive High-Speed Serial Configuration
Receive High-Speed Serial Cell Filtering Configuration/Status
Receive High-Speed Serial Interrupt Enables
Receive High-Speed Serial Interrupt Status
Receive High-Speed Serial HCS Error Count
Receive High-Speed Serial Cell Counter (LSB)
Receive High-Speed Serial Cell Counter
Receive High-Speed Serial Cell Counter (MSB)
Receive High-Speed Serial FIFO Overflow
Upstream Round Robin Weight
Logical Channel Base Address
Logical Channel Address Range / Logical Channel Base Address
MSB
0x00C
0x00D
0x00E
0x00F
0x010
0x011
0x012
0x013
0x014
0x015
0x016
0x017
0x018
Downstream Logical Channel FIFO Control
Downstream Logical Channel FIFO Interrupt Status
Reserved
Downstream Logical Channel FIFO Ready Level
Transmit High-Speed Serial Configuration
Transmit High-Speed Serial Cell Count Status
Transmit High-Speed Serial Cell Counter (LSB)
Transmit High-Speed Serial Cell Counter
Transmit High-Speed Serial Cell Counter (MSB)
Serial Link Maintenance
Reserved
Transmit Bit Oriented Code
Bit Oriented Code Receiver Enable
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
53
PMC [ PMC-SIERRA, INC ]
