RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
master as a single cell stream. Scheduling from the S/UNI-VORTEX onto the
upstream bus is described more fully in Section 9.1.2 on Page 32.
In aggregate, the 8 upstream links can burst data into the S/UNI-VORTEX at up
to 1.6 Gbps, which is twice the maximum bandwidth of the upstream bus.
Further, the bus master may be servicing several S/UNI-VORTEX devices at
once or be otherwise restricted in the maximum sustained bandwidth it is able to
receive from the S/UNI-VORTEX. Therefore, the potential to overflow one or
more of the 6 cell upstream FIFOs is a real possibility.
When any upstream FIFO has less than three empty cell buffers, it deasserts the
cell available (CA[0]) bit sent in the system overhead of the corresponding
downstream LVDS link (see Table 2). It is the responsibility of the far end device
(typically a S/UNI-DUPLEX) to start sending stuff cells immediately upon
indication that the S/UNI-VORTEX can accept no more traffic. By setting the full
mark at 3 cells the S/UNI-VORTEX allows for up to two additional cells can be
accepted after the cell available bit is deasserted. This accommodates far-end
latency in reaction to the CA[0] indication.
9.4 Timing Reference Insertion and Recovery
The high-speed LVDS links are capable of transporting a timing reference in both
directions, independent of the LVDS bit rate. As shown in Table 2, every cell
transmitted over the LVDS contains a timing reference field called TREF[5:0].
Although the timing reference is targeted at a typical need of transporting an 8
kHz signal, its frequency is not constrained to 8 kHz. Any frequency less than
the cell rate is permissible.
In the transmit direction, rising edges on the TX8K input are encoded in the cells
transmitted on all eight serial links. For each of the 8 LVDS links, the rising edge
of TX8K causes an internal counter to be initialized to the cell length minus 1.
The counter decrements with each subsequent byte transmitted until the fourth
byte of the next extended cell, at which point the state of the counter is written
into the outgoing TREF[5:0] field. If no rising edge on TX8K has occurred,
TREF[5:0] is set to all ones.
In the receive direction the S/UNI-VORTEX is typically receiving cells from a
S/UNI-DUPLEX device, which implements the same TX8K process described
above. As determined by the value of the RX8KSEL[2:0] bits in the Master
Configuration register, the timing signal received over one of the eight LVDS links
is recreated on RX8K.
The S/UNI-VORTEX monitors the TREF[5:0] field on the selected upstream
LVDS link and initializes an internal counter to the value of TREF[5:0] each time
the field is received. The counter decrements with each subsequent byte
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
46
PMC [ PMC-SIERRA, INC ]
