RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
As shown in Table 2, each cell transmitted over each of the eight upstream LVDS
upstream links contains 16 bits of information that convey the far-end cell buffer
status (full or not full) for 16 of the maximum 32 active PHYs supported on each
link. After two cells are received on the upstream link the downstream buffer
status of all 32 far-end PHYs has been updated. A separate overhead bit per cell
conveys the buffer status of the far-end microprocessor port.
Hence, at any given instant the S/UNI-VORTEX is using information that is either
one or two cells out of date. The far-end device (typically the S/UNI-DUPLEX) is
therefore required to have enough per PHY buffer space to accommodate the
slight delay in conveying the “buffer full” information to the S/UNI-VORTEX. The
S/UNI-VORTEX uses the full or not full information to determine which channels
should be involved in the current round of scheduling, as discussed above.
9.3.2 Upstream Traffic Flow Control
The upstream traffic flow control within the S/UNI-VORTEX allows for some
system engineering flexibility. When the system is engineered such that
maximum aggregate burst upstream bandwidth is less than or equal to the link
and device bandwidth at each stage of concentration, congestion will not occur
prior to upstream traffic queuing in the TM device1. In this case, upstream traffic
flow control is unnecessary and will not be utilized within the S/UNI-DUPLEX or
S/UNI-VORTEX devices.
However, when a system is engineered such that upstream burst bandwidth
capacity can exceed the link and bus bandwidth, then depending on the over
subscription employed, misbehaving users, and traffic burst scenarios,
congestion at the upstream S/UNI-VORTEX buffers can occur. To ensure that
these buffers do not overflow, upstream traffic flow control is implemented by the
S/UNI-VORTEX and S/UNI-DUPLEX.
Far-end scheduling of the up to 32 upstream PHY channels and the
microprocessor channel onto the upstream LVDS link is discussed in the S/UNI-
DUPLEX Data Sheet. This section discusses how upstream flow control is
implemented to prevent overflow of the S/UNI-VORTEX’s upstream FIFOs.
Unlike the downstream direction, the upstream direction does not require per
channel buffering or per channel buffer status indication. In the S/UNI-VORTEX,
each of the 8 upstream LVDS serial links is provided with a simple six cell FIFO.
The SCI-PHY/Any-PHY bus slave state machine services the 8 FIFOs with a
weighted round-robin algorithm and presents the data to the upstream bus
1
Upstream queues could congest due to restricted up-link capacity, in which case appropriate congestion
management algorithms within the TM device should be invoked.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
45
PMC [ PMC-SIERRA, INC ]
