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PM7351-BGI 参数 Datasheet PDF下载

PM7351-BGI图片预览
型号: PM7351-BGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA304, 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 174 页 / 1840 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7351 S/UNI-VORTEX  
DATA SHEET  
PMC-1980582  
ISSUE 5  
OCTAL SERIAL LINK MULTIPLEXER  
9.6.3.2 Reading Cells  
By default, control cells are not terminated by the Microprocessor Cell Buffer, but  
instead routed to the SCI-PHY/Any-PHY interface along with all other cells.  
Control cells that are routed to the SCI-PHY/Any-PHY bus will be stripped or  
padded (if required) to match the cell format of the bus.  
The redirection of control cells must be enabled by the ROUTECC register bit in  
the Master Configuration register. If ROUTECC is a logic 1, all cells received on  
the high-speed serial link with binary 111110 in the PHYID[5:0] prepend field will  
be routed to the Microprocessor Cell Buffer. The buffer has a capacity of four  
cells dedicated to each high-speed link. The control channel is flow controlled to  
avoid cell loss.  
A maskable interrupt status bit is set upon the receipt of a cell. The format of  
received cell when it is read from the Microprocessor Cell Buffer Data register is  
shown in Fig. 7. Unused bytes have undefined value. The value of the optional  
bytes depends on the configuration of the corresponding LVDS link and the  
source of the cell. Control cells that come from the far-end SCI-PHY/Any-PHY  
bus will have their optional fields defined only if both the SCI-PHY/Any-PHY bus  
and the LVDS link have been configured to carry them. Control cells that come  
from the far-end microprocessor port have their optional fields defined (i.e. equal  
to the value originally written by the far-end microprocessor) only if the LVDS link  
has been configured to carry them. This is discussed further in the Operations  
section.  
See the Operation section for details on the cell read protocol.  
9.7 Internal Registers  
The microprocessor interface provides access to normal and test mode registers.  
The normal mode registers are required for mission mode operation, and test  
mode registers are used to enhance the testability of the S/UNI-VORTEX. The  
register set is accessed as follows:  
9.8 Register Memory Map  
Address  
0x000  
0x001  
0x002  
0x003  
0x004  
Register  
Master Reset and Identity / Load Performance Meters  
Master Configuration  
Receive Serial Interrupt Status  
Transmit Serial Interrupt Status  
Miscellaneous Interrupt Statuses  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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