RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
received. When the count becomes zero, a rising edge is generated on RX8K.
If the value of TREF[5:0] is all ones, RX8K remains low. RX8K is left asserted
for two high speed (REFCLK) reference clock periods, and then it is deasserted.
The recovered timing event is generated one cell period later than the inserted
timing with a resolution of one byte. Because of the limited resolution, some
jitter is present. At a link rate of 155.52 Mb/s, 63ns of peak-to-peak jitter will
occur on RX8K. An external local high-Q phase locked loop (PLL) can be used
to remove the jitter.
9.5 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan.
The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The S/UNI-VORTEX identification code is 173510CD
hexadecimal.
9.6 Microprocessor Interface
The microprocessor interface is provided for device configuration, control and
monitoring by an external microprocessor. Normal mode registers and test mode
registers can be accessed through this port. Test mode registers are used to
enhance the testability of the S/UNI-VORTEX.
The interface has an 8-bit wide data bus. Multiplexed address and data
operation is supported.
9.6.1 Inband Communication Channel
To provide flexibility, two mechanisms are being provided for the transport of a
control channel. Control channel cells can be inserted and extracted either via
the microprocessor interface or via an external device transferring control
channel cells across the SCI-PHY/Any-PHY interfaces.
The control channel cell insertion and extraction capabilities provide a simple
unacknowledged (but flow controlled) cell relay capability. For a fully robust
control channel implementation, it is assumed the local microprocessor and the
remote entity are running a reliable communications protocol.
9.6.2 Insertion and Extraction Via the SCI-PHY/Any-PHY Interfaces
Control channel cells inserted via the downstream Any-PHY interface are treated
in the same manner as normal data traffic with respect to flow control, buffering,
and cell format.. The transmitting of control cells across the high-speed serial
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
47
PMC [ PMC-SIERRA, INC ]
