RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Byte
Bits
5:0
Mnemonic
Description
The transmitted ACTIVE bit is set by the
per-link ACTIVE register bits. To confirm
which link is active, the received ACTIVE
bit will be a one if the associated link is
selected by the S/UNI-DUPLEX.
In the event of an errored header or out of
cell delineation state, the previous ACTIVE
value is retained.
The timing reference encodes an 8 kHz
signal inband that is independent of the
serial bit rate.
3
TREF[5:0]
The TREF[5:0] binary value represents the
number of high-speed link bytes after this
one at which the timing reference is
inferred. An all ones value indicates no
timing mark is associated with this cell.
The transmitter outputs are internally terminated current mode drivers. Correct
termination at the receiver is required to provide the correct signal levels..
The internal transmit clock is synthesized from a 12.5 MHz to 25 MHz clock. The
resulting data bit rate is eight times the frequency of the REFCLK input. All jitter
below 1 MHz on REFCLK is passed unattenuated to the TXDn+/- outputs. The
design of the loop filter and PLL is optimized for minimum intrinsic jitter. With a
jitter free reference input and a low noise board layout, the intrinsic jitter is
typically less than 0.01 UI RMS and 0.10 UI peak-to-peak when measured using
a band pass filter with 12 kHz and 1.3 MHz cutoff frequencies.
The eight truly differential receivers are capable of handling signal swings down
to 100mV. A wide common mode range makes them compatible with LVDS
signals. External termination resisters must be provided to match the cable
impedance.
The receivers monitor for loss of signal (LOS) on the links. LOS is declared
upon 2048 bit periods (13.2 µs at 155.52 Mb/s) without a signal transition in the
scrambled data. As a consequence, a status bit is set, a maskable interrupt is
asserted and the RDI codeword is sent repetitively in the BOC bit in the
corresponding downstream link. The LOS indication is cleared when a signal
transition has occurred in each of 16 consecutive intervals of 16 bit periods each.
Clock recovery is performed by a digital phase locked loop (DPLL). The
implementation is robust against operating condition variations and power supply
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
37
PMC [ PMC-SIERRA, INC ]
