RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
9.2 High-Speed Serial Interfaces
The S/UNI-VORTEX provides backplane interconnection via 100 to 200 Mb/s
serial links. All data destined to and coming from the line cards are concentrated
on these high-speed links. The transceivers support UTP-5 cable lengths up to
10m. To avoid clock skew issues, no clock is transmitted and the receivers
recover a local clock from the incoming data.
The serial links typically carry ATM cells with prepended bytes. The cell format is
illustrated in Fig. 4. The S/UNI-VORTEX appends the first four bytes and the
Header Check Sequence (HCS) byte in the downstream direction and strips
them off and parses them in the upstream direction. The remainder of the bytes
in the data structure is transferred transparently. The bytes are serialized most
significant bit first.
The bit stream is a simple concatenation of the extended cells. Cell rate
decoupling is accomplished through introduction of stuff cells.
The transmitter inserts a correct CRC-8 that protects both the ATM cell header
and prepended bytes in the HCS byte. The receiver uses the HCS byte for
delineation. Failure to establish cell alignment results in a loss of cell delineation
(LCD) alarm. The entire bit stream is scrambled with a x43 + 1 self-synchronous
scrambler.
Table 2 summarizes the contents of the system prepended bytes.
Fig. 4 High-Speed Serial Link Data Structure
Byte
0
1
2
3
4+N
User Header
4 to 6 bytes
H
C
S
ATM Payload
48 bytes
ATM Payload
System
Prepend
User
Prepend
N bytes, where N = 0 or 2
Table 2 Prepended Fields
Byte
Bits
Mnemonic
Description
0
7:0
CA[15:8]
The CA[15:0] bits carry logical channel
flow control information in the upstream
direction. To support 32 logical channels,
the status for each logical channel is sent
every other cell; the CASEL indicates
1
7:0
CA[7:0]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PMC [ PMC-SIERRA, INC ]
