RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Byte
Bits
Mnemonic
Description
which half is represented. If CASEL is
logic 0, CA[15:0] corresponds to those
logical channels with UTOPIA addresses 0
through 15. If CASEL is logic 1, CA[15:0]
corresponds to those logical channels with
UTOPIA addresses 16 through 31.
In the downstream direction, CA[0] is the
only relevant bit and it flow controls the
aggregate. A logic 0 indicates the far end
can accept no more cells, and the S/UNI-
DUPLEX will immediately start sending idle
cells. If this bit is a logic 1, the S/UNI-
DUPLEX is free to send all queued traffic.
To allow inter-operability with a device that
may be flow controlled on a logical channel
basic, CA[15:1] are set to the same state
as CA[0].
In the event of an errored header (as
detected by an incorrect HCS), the CA bits
will be assumed to be all zero. This
ensures cells are not transmitted for which
there is no buffer space.
2
2
7
6
CASEL
UPCA
The state of the CA select bit determines
which half of the modems the CA[15:0] bits
correspond to. CASEL toggles with each
cell transmitted.
The UPCA bit carries flow control
information for the microprocessor control
channel. If this bit is one, control channel
cells may be transferred.
In the event of an errored header, the
UPCA bit will be assumed to be zero. This
ensures cells are not transmitted for which
there is no buffer space.
2
5:0
PHYID
The PHY identifier determines to which
PHY a cell is destined in the downstream
direction and from which PHY it came in
the upstream direction. It also indicates
whether the cell is a stuff or control
channel cell. The field is encoded as
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
35
PMC [ PMC-SIERRA, INC ]
